1. Filed of the Invention
The present invention relates to a small semiconductor integrated circuit device having a large storage capacity. More particularly, the present invention relates to a dynamic random-access memory (hereinafter, abbreviated to xe2x80x9cDRAMxe2x80x9d) suitable for use in a high-degree integrated circuit device.
2. Description of the Related Arts
The degree of integration of DRAMs has been quadrupled in three years and demand for DRAMs has progressively increased owing to the recent booming demand for personal computers.
Memory cells of a DRAM are arranged in either a folded bit line arrangement or an open bit line arrangement. FIG. 1 shows the typical layout of the memory cells of a DRAM of a typical folded bit line structure. In this DRAM, word lines and bit lines of a width F are arranged at pitches 2F to arrange the memory cells in the least possible area. Two memory cells are formed in a laterally elongate active region, and the two memory cells use a common longitudinally elongate bit line contact. FIG. 2 shows the typical layout of the memory cells of a DRAM of a typical open bit line structure mentioned in xe2x80x9c1993 Symposium on VLSI Circuitsxe2x80x9d p. 91. In this DRAM, word lines of a width F are arranged at pitches 2F, and bit lines of a width F are arranged at pitches 3F. Let us examine a data read process of reading data from those DRAMs of two different bit line structures. When one of the word lines of the DRAM in the folded bit line structure is turned on, data can be read from the alternate bit lines. As shown in FIG. 3(a), two paired bit lines connected to a sense amplifier are two adjacent bit lines in the same mat. Thus, the arrangement of the memory cells is called a folded bit line structure. When one of the word lines of the DRAM of the open bit line structure is turned on, data can be read from all the bit lines, and two paired bit lines are in different mats as shown in FIG. 3(b). Whereas the driven word line coupled with the paired bit lines is common in the folded bit line structure, the same is not common in the open bit line structure. In terms of noise, word line driving noise is cancelled between the paired bit lines in the folded bit line structure and the same is not cancelled in the open bit line structure, which signifies that the folded bit line structure is unsusceptible to noise. Although the open bit line structure is susceptible to noise, it is a significant feature of the open bit line structure that the cells can be arranged in a small area. Whereas one cell needs an area of 8F2 in the folded bit line structure as shown in FIG. 1, one cell needs an area of 6F2 in the open bit line structure as shown in FIG. 2.
In view of mass production, the reduction of the area of a chip, i.e., the reduction of the area of a region for memory cell arrangement, is very effective in reducing the cost of the product. From such a point of view, the open bit line structure is more desirable than the folded bit line structure. However, it is a problem in employing the open bit line structure how far the noise resistance of the open bit line structure can be improved. Practically, the open bit line structure has been employed in DRAMs of generations up to a 16 kB-generation. However, recent DRAMs of advanced generations employ the folded bit line structure.
A DRAM having memory cells arranged in the open bit line arrangement of a structure similar to that shown in FIG. 2 is proposed in Japanese Patent Laid-Open No. Hei 07-066299. Although this prior art DRAM has a memory cell typical layout closely resembling the memory cell typical layout shown in FIG. 2, the bit lines of this DRAM are arranged at pitches 4F. Thus, the lower electrode contact holes for capacitors are arranged at increased intervals to reduce current leakage across the memory cells.
The following problems reside in the foregoing prior art DRAMs.
The DRAM mentioned in xe2x80x9c1993 Symposium on VLSI Circuitsxe2x80x9d has the following problems. As obvious from FIG. 2, the lower electrode contact holes 5 for the capacitors are close to the bit lines 3. The so-called self-alignment techniques are essential to forming the lower electrode contact holes 5 for the capacitors so that the lower electrode contact holes 5 may not touch the bit lines 3. A bit line forming process and those following the bit line forming process will be explained with reference to a section taken on line Axe2x80x94A in FIG. 2. As shown in FIG. 4, bit line contact plugs 10 are formed and then a two-layer film of a tungsten film and a silicon nitride film for forming bit lines are deposited. The two-layer film is processed by a lithographic process and a dry etching process to form bit lines 11 as shown in FIG. 5. A silicon nitride film 1201 is deposited as shown in FIG. 6, and a layer insulating film 901 of silicon oxide is formed in a flat surface over the silicon nitride film 1201. Lower electrode contact holes for the capacitors are formed by an etching process having a high silicon nitride selectivity. Then, plugs 13 are formed as shown in FIG. 7. Thus, the lower electrode contact holes can be formed by a self-alignment contact hole forming technique so that the lower electrode contact do not touch the bit lines 11. Even if a sufficient allowance is unavailable, the contact holes can be formed without increasing area by the self-alignment contact hole forming technique. However, the self-alignment contact hole forming technique has the following problems. The dielectric constant of silicon nitride is about twice that of silicon oxide. The self-alignment contact hole forming technique shown in FIG. 7 surrounds the bit line 11 by silicon nitride 12 and 1201 and insulate the bit line 11 from the lower electrode plug by silicon nitride, which increases bit line capacitance. As mentioned above, the open bit line structure is more susceptible to noise than the folded bit line structure. Therefore, it is very important to reduce bit line capacitance when the open bit line structure is employed. Therefore, it is inappropriate to apply the self-alignment contact hole forming technique to fabricating a DRAM of the open bit line structure.
In the DRAM proposed in Japanese Patent Laid-Open No. Hei 07-066299, the memory cells are arranged in the open bit line arrangement similar to that shown in FIG. 2 and the bit lines are arranged at increased pitches to space the lower electrode contact holes for capacitors wide apart. Therefore, the memory cell area increases and the DRAM is unable to make the most of the characteristic advantage of the open bit line arrangement.
The present invention has been made in view of those problems in the prior art and it is therefore an object of the present invention to provide a semiconductor integrated circuit device having a small bit line capacitance, excellent in noise resistance, requiring a small cell area and having bit lines arranged in an open bit line arrangement, and to provide a method of fabricating such a semiconductor integrated circuit device.
Typical summaries of the invention is disclosed in this application will be described as follows.
According to a first aspect of the present invention, a semiconductor integrated circuit device having a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells each having a transistor and a capacitor placed on the bit line comprises: active regions formed in a surface of a semiconductor substrate, intersecting adjacent first and second word lines among the plurality of word lines and first bit lines among the plurality of bit lines, extending in a third direction different from the first and the second direction and having a predetermined width along a fourth direction perpendicular to the third direction; first and second semiconductor regions formed in the active regions and serving as sources and drains of the transistors; a first electrode(capacitor lower electrode) and a second electrode(plate) for the capacitors; a dielectric film formed between the first and the second electrodes of the capacitors; a first insulating film formed between the bit lines and the first electrodes(capacitor lower electrode); and a first conducting layer(SNCT) having portions formed in first openings formed in the first insulating film and electrically connecting the first(source) or the second semiconductor regions(drain) to the first electrodes serving as the lower electrodes of the capacitors; wherein portions of the first conducting layer are arranged in regions surrounded by the word lines and the bit lines, respectively, and the centers of the portions of the first conducting layers(SNCT) are dislocated from positions on the center lines of the active regions extending in the third direction.
According to a second aspect of the present invention, a semiconductor integrated circuit device comprises: adjacent first and second word lines extending in a first direction; third word lines disposed adjacent to the first word lines opposite to the second word lines with respect to the first word lines; fourth word lines disposed adjacent to the second word lines opposite to the first word lines with respect to the second word lines; adjacent first, second and third bit lines extending in a second direction intersecting the first direction; active regions extending in a third direction intersecting the first and the second direction; first semiconductor regions formed in the active regions between the first and the second word lines; second semiconductor regions formed in the active regions between the first and the third word lines and between the second and the fourth word lines; first and second electrodes for forming capacitors; a dielectric film formed between the first and the second electrodes; and a plurality of first conducting layers having portions electrically connecting the second semiconductor regions to the first electrodes; wherein the portions of the first conducting layers are formed in regions surrounded by the word lines and the bit lines, respectively, an angle between a straight line connecting the center of each portion of the first conducting layer disposed between the first and the third word lines to the center of each portion of the first conducting layer disposed between the second and the fourth word lines and the first direction is smaller than an angle between the third direction and the first direction.
According to a third aspect of the present invention, a semiconductor integrated circuit device having a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells each including a transistor and a capacitor disposed on the bit line comprises: active regions formed on a semiconductor substrate, extending in a third direction different from the first and the second directions and each intersecting the two word lines and the one bit line; first and second semiconductor regions formed in the active regions and serving as sources and drains of the transistors; first and second electrodes for forming the capacitors; a dielectric film formed between the first and the second electrodes; a first insulating film formed between the bit lines and the first electrodes; and a first conducting layer having portions formed in first openings formed in the first insulating film and electrically connecting either of the first and the second semiconductor regions to the first electrodes; wherein portions of the first conducting layer are arranged in regions surrounded by the word lines and the bit lines, respectively, and the portions of the first conducting layer has a width in the second direction smaller than that of the word lines.
According to a fourth aspect of the present invention, a semiconductor integrated circuit device having a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells each including a transistor and a capacitor disposed on the bit line comprises: first and second electrodes for forming the capacitors formed on a semiconductor substrate; a dielectric film formed between the first and the second electrodes; a first insulating film formed between the bit lines and the first electrodes; and a first conducting layer having portions formed in first openings formed in the first insulating film and electrically connecting the transistors to the first electrodes; wherein portions of the first conducting layers are arranged in regions surrounded by the word lines and the bit lines, respectively, and the bit lines have a width smaller than that of the word lines.
According to a fifth aspect of the present invention, a semiconductor integrated circuit device fabricating method comprises the steps of: adjacently forming first, second and third conducting layers on a semiconductor substrate; forming a first insulating film over the upper surfaces and the side walls of the first, the second and the third conducting layers; forming a second insulating film over the first insulating film so as to fill up gaps between the first, the second and the third conducting layers; forming first openings in the first and the second insulating film so that portions of the surface of the semiconductor substrate between the first and the second conducting layers are exposed; forming a fourth conducting layer so as to fill up the first openings; forming second openings in the first and the second insulating films so that portions of the surface of the semiconductor substrate between the second and the third conducting layer are exposed; and forming a fifth conducting layer so as to fill up the second openings.
According to a sixth aspect of the present invention, a semiconductor integrated circuit device fabricating method comprises the steps of: forming first and second conducting layers in a memory cell forming regions on a semiconductor substrate and forming a third conducting layer in a peripheral circuit forming region on the semiconductor substrate; forming a first insulating film over the first, the second and the third conducting layers in a thickness such that a gap between the first and the second conducting layers is not filled up; forming a second insulating film over the first, the second and the third conducting layer in a thickness such that the gap between the first and the second conducting layers is filled up; forming a third insulating film over the memory cell forming region; and forming a side wall insulating film over the side walls of the third conducting layer by subjecting portions of the first and the second insulating films formed over the third conducting layer to anisotropic etching.
The semiconductor integrated circuit device having the foregoing construction and formed by the foregoing method has a small bit line capacity, is excellent in noise resistance and has a small cell area.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.